Patent Number: 6,255,172

Title: Electrically erasable non-volatile memory

Abstract: A method of manufacturing an electrically erasable non-volatile memory is suitable for use on a substrate. The method includes the following steps. First, a tunnel oxide layer is formed on the substrate. A floating gate and a silicon oxide layer/silicon nitride/silicon oxide layer is formed in order on the tunnel oxide layer. Next, a first oxide layer and a silicon nitride spacer are formed in order on the sidewalls of the floating gate. A second oxide layer is formed along the surface of the above entire structure. A third oxide layer is formed on the substrate on both sides of the silicon nitride spacer by oxidation. A patterned conductive layer on the substrate to serve as a control gate and a select transistor gate is formed above the substrate. Using the select transistor gate as a mask, the exposed part of the third oxide layer is removed to make the residual third oxide layer serve as a gate oxide layer of the select transistor. Finally, ion implantation is performed on the substrate to form source and drain regions.

Inventors: Huang; Chih-Jen (Hsinchu, TW), Wu; Auter (Yun-Lin Hsien, TW), Hong; Shih-Fang (Kaohsiung, TW)

Assignee: United Microelectronics Corp.

International Classification: H01L 21/336 (20060101); H01L 21/02 (20060101); H01L 21/28 (20060101); H01L 021/824 ()

Expiration Date: 07/03/2018