Patent Number: 6,255,175

Title: Fabrication of a field effect transistor with minimized parasitic Miller capacitance

Abstract: A field effect transistor is fabricated to have a drain overlap and a source overlap to minimize series resistance between the gate and the drain and between the gate and the source of the field effect transistor. The parasitic Miller capacitance formed by the drain overlap and the source overlap is reduced by forming a depletion region at the sidewalls of the gate structure of the field effect transistor. The depletion region at the sidewalls of the gate structure is formed by counter-doping the sidewalls of the gate structure. The sidewalls of the gate structure at the drain side and the source side of the field effect transistor are doped with a type of dopant that is opposite to the type of dopant within the gate structure. Such dopant at the sidewalls of the gate structure forms a respective depletion region from the sidewall into approximately the edge of the drain overlap and source overlap that extends under the gate structure to reduce the parasitic Miller capacitance formed by the drain overlap and the source overlap.

Inventors: Yu; Bin (Sunnyvale, CA)

Assignee: Advanced Micro Devices, Inc.

International Classification: H01L 21/02 (20060101); H01L 21/28 (20060101); H01L 29/49 (20060101); H01L 21/265 (20060101); H01L 29/40 (20060101); H01L 21/336 (20060101); H01L 021/336 ()

Expiration Date: 07/03/2018