Patent Number: 6,255,176

Title: Method of forming trench for semiconductor device isolation

Abstract: A method of forming a trench for semiconductor device isolation includes the steps of making a trench at a device isolation area of a silicon wafer overlaid with a pad oxide and a nitride through photolithography and etching, forming a liner oxide at an inner wall of the trench, filling the trench through depositing an insulating layer onto the entire surface of the silicon wafer, densifying the insulating layer, and planarizing the densified insulating layer such that the insulating layer is left only at the inside of the trench. The step of forming the liner oxide includes the sub-steps of forming a first liner oxide through performing rapid thermal processing with respect to the silicon wafer with the trench, forming a second liner nitride on the first liner oxide through performing the rapid thermal processing with respect to the silicon wafer with the first liner oxide, and forming a third liner wet oxide on the second liner nitride through performing the rapid thermal processing with respect to the second liner nitride. The trench so formed has removed corners. The three rapid thermal processing may be performed in situ in a single rapid thermal processing machine without exposing the wafers to atmosphere.

Inventors: Kim; Seo-Won (Seoul, KR), Hyun; Yun-Woong (Seoul, KR)

Assignee: Anam Semiconductor Inc.

International Classification: H01L 21/762 (20060101); H01L 21/70 (20060101); H01L 021/336 (); H01L 021/76 ()

Expiration Date: 07/03/2018