Patent Number: 6,255,177

Title: Method for fabricating a salicide gate

Abstract: A fabrication method for a salicide gate is described, wherein the method comprising forming a gate structure on a substrate. The gate structure comprises a polysilicon gate and a selective-deposition dummy layer formed on the polysilicon gate. Source/drain regions are then formed on both sides of the gate structure in the substrate. After this, a dielectric layer is selectively deposited on the substrate, wherein the dielectric layer on the source/drain regions is thicker than the dielectric layer on the anti-reflection layer. A portion of the dielectric layer is removed until the anti-reflection layer is exposed. The anti-reflection layer is subsequently removed, followed by forming a salicide layer on the polysilicon gate to complete the manufacturing of a salicide gate.

Inventors: Fang; Edberg (Yuanlin Hsien, TW), Hsieh; Wen-Yi (Hsinchu, TW)

Assignee: United Microelectronics Corp.

International Classification: H01L 21/02 (20060101); H01L 21/28 (20060101); H01L 21/336 (20060101); H01L 021/336 ()

Expiration Date: 07/03/2018