Patent Number: 6,255,178

Title: Method for forming transistors with raised source and drains and device formed thereby

Abstract: The preferred embodiment of the present invention provides a transistor structure and method for fabricating the same that overcomes the disadvantages of the prior art. In particular, the preferred structure and method results in lower leakage and junction capacitance by using raised source and drains which are partially isolated from the substrate by a dielectric layer. The raised source and drains are preferably fabricated from the same material layer used to form the transistor gate. The preferred method for fabricating the transistor uses hybrid resist to accurately pattern the gate material layer into regions for the gate, the source and the drain. The source and drain regions are then connected to the substrate by growing silicon. The preferred method thus results in an improved transistor structure while not requiring excessive fabrication steps.

Inventors: Brown; Jeffrey S. (Middlesex, VT), Dunn; James S. (Jericho, VT), Holmes; Steven J. (Milton, VT), Horak; David V. (Essex Junction, VT), Leidy; Robert K. (Burlington, VT), Voldman; Steven H. (South Burlington, VT)

Assignee: International Business Machines Corp.

International Classification: G03F 7/38 (20060101); H01L 21/336 (20060101); H01L 21/02 (20060101); H01L 21/027 (20060101); H01L 21/311 (20060101); G03F 7/095 (20060101); H01L 21/265 (20060101); H01L 021/336 ()

Expiration Date: 07/03/2018