Patent Number: 6,255,180

Title: Semiconductor device with outwardly tapered sidewall spacers and method for forming same

Abstract: The present invention advantageously provides a method for forming a nitride sidewall spacer having a relatively thin upper portion and a lower portion that increases in lateral thickness as it substantially tapers toward an underlying surface. In an embodiment, nitride sidewall spacers having this shape are formed upon the opposed sidewall surfaces of gate conductors which are dielectrically spaced above a semiconductor substrate. The upper portion of each spacer is bounded by a substantially vertical upper outer surface while the lower portion is bounded by a lower outer surface which is angled away from the upper outer surface. A unitary source/drain implant may be forwarded into the substrate to form graded junctions. The implant is self-aligned to the upper outer surfaces of the nitride spacers. As such, the graded junctions are displaced laterally from the gate conductors by a distance which is dictated by the lateral thickness of the upper portion of each spacer. The graded junctions include inner regions which are shallower than, and have a lower concentration of dopant than, outer regions spaced from the gate conductor by the lower portions of the spacers.

Inventors: Smith; Eugene C. (Apple Valley, MN)

Assignee: Cypress Semiconductor Corporation

International Classification: H01L 21/336 (20060101); H01L 21/02 (20060101); H01L 21/266 (20060101); H01L 21/60 (20060101); H01L 021/336 ()

Expiration Date: 07/03/2018