Patent Number: 6,255,181

Title: Method for fabricating MOS semiconductor device having salicide region and LDD structure

Abstract: A method for fabricating a MOS transistor involves forming a buffering layer on an active region, performing an ion implantation to form a heavily doped region (source/drain region), and forming a self-aligned silicide region (salicide region) on exposed silicon and polysilicon gate. With this method, a salicide region free from voids can be formed because transition metal material (for example, cobalt) and silicon atoms at an interface portion between the transition metal layer and the substrate silicon are not locally accelerated or delayed during the formation of the salicide region.

Inventors: Song; Oh-Sung (Seoul, KR), Ku; Ja-Hum (Kyunggi-do, KR)

Assignee: Samsung Electronics Co., Ltd.

International Classification: H01L 21/336 (20060101); H01L 21/02 (20060101); H01L 21/285 (20060101); H01L 21/265 (20060101); H01L 021/336 ()

Expiration Date: 07/03/2018