Patent Number: 6,255,182

Title: Method of forming a gate structure of a transistor by means of scalable spacer technology

Abstract: A method is described which can be used to form gate structures of very small dimensions in a semiconductor device. The method may be used to avoid employment of highly-sophisticated and cost-intensive DUV photolithography. In one illustrative embodiment, the method comprises forming a gate electrode layer, forming a first mask layer above the gate electrode layer, and forming a sidewall spacer adjacent the sidewalls of the first mask layer. Thereafter, the method comprises forming a second mask layer above a portion of the sidewall spacer and the first mask layer, removing portions of the sidewall spacer to define a hard mask comprised of a portion of the sidewall spacer, and patterning the gate electrode layer using the hard mask to define a gate electrode of the device.

Inventors: Wieczorek; Karsten (Reichenberg-Boxdorf, DE), Horstmann; Manfred (Dresden, DE), Hause; Frederick N. (Austin, TX)

Assignee: Advanced Micro Devices, Inc.

International Classification: H01L 21/02 (20060101); H01L 21/28 (20060101); H01L 21/336 (20060101); H01L 021/336 ()

Expiration Date: 07/03/2018