Patent Number: 6,255,183

Title: Manufacture of a semiconductor device with a MOS transistor having an LDD structure using SiGe spacers

Abstract: A method of manufacturing a semiconductor device with a MOS transistor having an LDD structure. A gate dielectric (6) and a gate electrode (7, 8) are formed on a surface (5) of a silicon substrate (1). The surface adjacent the gate electrode is then exposed, and a layer of semiconductor material (10) is formed on an edge (9) of the surface adjoining the gate electrode. Ions (13, 14) are subsequently implated, with the gate electrode and the layer of semiconductor material acting as a mask. Finally, a heat treatment is carried out whereby a source zone (16, 17) and a drain zone (18, 19) are formed through activation of the implanted ions and through diffusion of atoms of a dopant from the layer of semiconductor material. The portions (b) of these zones formed by diffusion are weakly doped here and lie between the more strongly doped portions (a) formed through activation of implanted ions and the channel zone (20, 21). An LDD structure has thus been formed. In the method, a layer of semiconductor material formed by Si.sub.1-x Ge.sub.x, 0.1<x<0.6, is provided on the edge adjoining the gate electrode. This layer is etched away selectively after the heat treatment. The formation of parasitic drain-gate capacitances is counteracted thereby.

Inventors: Schmitz; Jurriaan (Eindhoven, NL), Ponomarev; Youri V. (Eindhoven, NL), Woerlee; Pierre H. (Eindhoven, NL)

Assignee: U.S. Phillips Corporation

International Classification: H01L 21/225 (20060101); H01L 21/336 (20060101); H01L 21/02 (20060101); H01L 21/70 (20060101); H01L 21/28 (20060101); H01L 21/8238 (20060101); H01L 021/336 ()

Expiration Date: 07/03/2018