Patent Number: 6,255,184

Title: Fabrication process for a three dimensional trench emitter bipolar transistor

Abstract: A process for fabricating a bipolar junction transistor, featuring an N type, polysilicon emitter structure, located in an emitter trench, and featuring a narrow width. P type base region, located directly underlying an N type, emitter region, which is formed in the semiconductor substrate, along the vertical and horizontal sides of the emitter trench, has been developed. The process features forming an emitter trench in a semiconductor substrate, followed by a large angle ion implantation procedure, used to form a P type, base region, in an area of the semiconductor substrate located along the sides of the emitter trench. Formation of a polysilicon emitter structure, followed by an anneal cycle, create a narrow width, emitter region, underlying the polysilicon emitter structure, also resulting in the formation of a narrow width, P type base region, located between the overlying N type emitter region, and an underlying N type, epitaxial silicon layer.

Inventors: Sune; Ching-Tzong (Hsin-chu, TW)

Assignee: Episil Technologies, Inc.

International Classification: H01L 21/762 (20060101); H01L 21/02 (20060101); H01L 29/08 (20060101); H01L 21/70 (20060101); H01L 29/02 (20060101); H01L 21/763 (20060101); H01L 29/732 (20060101); H01L 29/423 (20060101); H01L 29/40 (20060101); H01L 29/66 (20060101); H01L 21/331 (20060101); H01L 29/417 (20060101); H01L 021/331 ()

Expiration Date: 07/03/2018