Patent Number: 6,255,186

Title: Methods of forming integrated circuitry and capacitors having a capacitor electrode having a base and a pair of walls projecting upwardly therefrom

Abstract: In accordance with one implementation the invention, a capacitor comprises two conductive capacitor electrodes separated by a capacitor dielectric layer, with at least one of the capacitor electrodes comprising at least one of Pt and Pd, and also comprising another metal which is capable of forming a conductive metal oxide when exposed to oxidizing conditions. In accordance with another. implementation, integrated circuitry includes a conductive silicon containing electrode projecting from a circuit node. A capacitor is received over the silicon containing electrode and comprises a first capacitor electrode having at least one of Pt and Pd, and also comprising another metal which is capable of forming a conductive metal oxide when exposed to oxidizing conditions. A high K capacitor dielectric layer received over the first capacitor electrode. A second capacitor electrode is received over the high K capacitor dielectric layer. In another implementation, a capacitor electrode comprises at least one of Pt and Pd and a conductive metal oxide, with the electrode having a base and a pair of walls projecting upwardly therefrom. The base has a greater concentration of the conductive metal oxide than any concentration of the conductive metal oxide in the walls. Methods of fabricating capacitors are also disclosed.

Inventors: Al-Shareef; Husam N. (Boise, ID), DeBoer; Scott Jeffery (Boise, ID), Thakur; Randhir P. S. (San Jose, CA)

Assignee: Micron Technology, Inc.

International Classification: H01L 21/02 (20060101); H01L 21/70 (20060101); H01L 21/8242 (20060101); H01L 021/20 ()

Expiration Date: 07/03/2018