Patent Number: 6,255,187

Title: Method of fabricating self-aligning stacked capacitor using electroplating method

Abstract: A method of fabricating a self-aligned stacked capacitor is provided, in which buried contacts and storage nodes are simultaneously formed by electroplating. In this method, a semiconductor substrate having exposed conductive areas is prepared for, and an interlayer insulative layer having buried contact holes that expose the conductive areas, is formed over the semiconductor substrate. A lower conductive seed layer is then formed over the entire surface of the innerwalls of the buried contact holes and the upper surface of the interlayer insulative layer. Non-conductor patterns having storage node holes that expose the buried contact holes, are then formed over the lower conductive seed layer on the upper surface of the interlayer insulative layer. A buried contact that fills the buried contact hole, and a lower electrode that fills the storage node hole, are then simultaneously formed by electroplating.

Inventors: Horii; Hideki (Kyungki-do, KR)

Assignee: Samsung Electronics Co., Ltd.

International Classification: H01L 21/288 (20060101); H01L 21/02 (20060101); H01L 21/70 (20060101); H01L 21/8242 (20060101); H01L 021/20 ()

Expiration Date: 07/03/2018