Patent Number: 6,255,190

Title: Method for dielectrically isolated deep pn-junctions in silicon substrates using deep trench sidewall predeposition technology

Abstract: A method for forming very deep pn-junctions without using epitaxy or extensively high temperature processing is provided. At least two parallel deep trenches are etched into a silicon substrate. Then the sidewalls of these trenches are predeposited by dopants. After filling the deep trenches with insulating material, a diffusion process is done. This diffusion process performs in such a way that the formerly predeposited dopant is distributed rather uniformly in between the parallel deep trenches, e.g. is counterdoping the whole region with respect to the monocrystalline silicon substrate. The said lateral trench doped region, which preferably is more deep than wide, serves either as drain or collector region of high voltage transistors or other high voltage devices. Also other devices like hall sensors, which gain advantages from the more deep than wide counterdoped regions, are possible.

Inventors: Kroner; Friedrich (Villach, AT)

Assignee: Austria Mikro Systeme International AG

International Classification: H01L 21/762 (20060101); H01L 21/70 (20060101); H01L 21/761 (20060101); H01L 21/763 (20060101); H01L 021/76 ()

Expiration Date: 07/03/2018