Patent Number: 6,255,191

Title: Method of fabricating an isolation structure in an integrated circuit

Abstract: A semiconductor fabrication method is provided for the fabrication of an isolation structure including a shallow-trench isolation (STI) structure in an integrated circuit. This method is characterized by the increase in the thickness of the adhesive layer over that of the prior art and also in the use of thermal oxidation process to form the STI structure. The thick adhesive layer can thus resist the stress from thermal expansion of the various component layers in the integrated circuit during heat treatment. Moreover, the resulting STI structure is not formed with recessed edge portions since the hydrofluoric (HF) etchant acts on the silicon dioxide plug in the STI structure with substantially the same etching rate as on the adhesive layer. Moreover, this method includes no chemical-mechanical polish (CMP) process, so the problem of scratches on the surface of the silicon dioxide plug as seen in the case of the prior art is avoided.

Inventors: Gau; Jing-Horng (Nan-Tou Hsien, TW), Huang; Hsiu-Wen (Kaoshiung, TW)

Assignee: United Microelectronics Corp.

International Classification: H01L 21/762 (20060101); H01L 21/70 (20060101); H01L 021/762 ()

Expiration Date: 07/03/2018