Patent Number: 6,255,202

Title: Damascene T-gate using a spacer flow

Abstract: A method for fabricating a T-gate structure is provided. A structure is provided that has a silicon layer having a gate oxide layer, a polysilicon layer over the gate oxide layer and an insulating layer over the gate oxide layer. An opening is formed extending partially into the insulating layer. The opening in the insulating layer extends from a top surface of the insulating layer to a first depth. Spacers are then formed on the sides of the opening. The opening is then extended in the insulating layer from the first depth to a second depth. The opening is wider from the top surface of the insulating layer to the first depth than the opening is from the first depth to the second depth. The spacers are then removed from the opening. The opening is then filled with a conductive material to form a T-gate structure.

Inventors: Lyons; Christopher F. (Fremont, CA), Subramanian; Ramkumar (San Jose, CA), Singh; Bhanwar (Morgan Hill, CA), Plat; Marina (San Jose, CA)

Assignee: Advanced Micro Devices, Inc.

International Classification: H01L 21/336 (20060101); H01L 21/02 (20060101); H01L 21/28 (20060101); H01L 29/423 (20060101); H01L 29/40 (20060101); H01L 21/70 (20060101); H01L 29/49 (20060101); H01L 21/768 (20060101); H01L 021/320 ()

Expiration Date: 07/03/2018