Patent Number: 6,255,203

Title: Technique for low-temperature formation of excellent silicided .alpha.-Si gate structures

Abstract: This application relates to a process to suppress the impurity diffusion through gate oxide on silicided amorphous-Si gate structures that utilize the silicide layers as the implantation barrier to minimize the impurity diffusion by reducing the projectile range and implant-induced defects, resulting in smaller flat-band voltage(V.sub.FB) shift and better characteristics of the breakdown field(E.sub.bd) and charge to breakdown(Q.sub.bd). In addition, the amorphous-Si underlying layer is simultaneously kept during the formation of a low-temperature self-aligned silicide (SAD) process to further retard the impurity diffusion. Hence, the usage of such bilayered silicide/amorphous-Si films could effectively retard the impurity diffusion, by combining both effects of the amorphous-Si layer and the silicide process or inducing other undesirable effects such as the increase of gate sheet resistance.

Inventors: Cheng; Huang-Chung (Hsinchu, TW), Lai; Wen-Koi (Hsinchu, TW), Chen; Nan-Ching (Hsinchu, TW)

Assignee: National Science Council

International Classification: H01L 21/336 (20060101); H01L 21/02 (20060101); H01L 21/28 (20060101); H01L 29/49 (20060101); H01L 29/40 (20060101); H01L 021/20 (); H01L 021/320 (); H01L 021/476 ()

Expiration Date: 07/03/2018