Patent Number: 6,255,207

Title: Composite planarizing dielectric layer employing high density plasma chemical vapor deposited (HDP-CVD) underlayer

Abstract: A method for forming upon a substrate employed within a microelectronics fabrication a composite dielectric layer having etched via contact holes in which via poisoning is attenuated. There is provided a substrate employed within a microelectronics fabrication. There is formed upon the substrate a patterned microelectronics layer. There is then formed upon the substrate a blanket silicon containing dielectric layer employing high density plasma chemical vapor deposition (HDP-CVD). There is then formed upon the blanket silicon containing glass dielectric layer a low dielectric constant dielectric layer over which is formed a silicon oxide dielectric cap layer to form a composite inter-level metal dielectric (IMD) layer. There is then etched through the composite IMD dielectric layer a series of via contact holes. The method of formation, surface profile and properties of the blanket silicon containing glass dielectric layer provides attenuated via poisoning after via hole etching.

Inventors: Jang; Syun-Ming (Hsin-Chu, TW)

Assignee: Taiwan Semiconductor Manufacturing Company

International Classification: H01L 21/70 (20060101); H01L 21/768 (20060101); H01L 021/44 ()

Expiration Date: 07/03/2018