Patent Number: 6,255,214

Title: Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of source and drain regions

Abstract: A method for forming ultra shallow junctions in a semiconductor wafer with reduced junction leakage arising from a silicidation process amorphizes the semiconductor material in the gate and source/drain junctions prior to the deposition of the metal during silicidation. After the gate and source/drain junctions are formed in a semiconductor device, non-dopant material, such as silicon or germanium, is implanted into the semiconductor material in an unmasked implantation procedure. This highly controllable implanting creates amorphous silicon regions with a substantially smooth interface with the crystalline silicon. When the silicide regions are formed during subsequent annealing steps, the silicide forms in a manner that follows the amorphous regions so that the silicide/silicon interface is also substantially smooth and junction leakage induced by silicidation is prevented.

Inventors: Wieczorek; Karsten (Reichenberg-Boxdorf, DE), Kepler; Nick (Saratoga, CA), Besser; Paul R. (Sunnyvale, CA)

Assignee: Advanced Micro Devices, Inc.

International Classification: H01L 21/02 (20060101); H01L 21/285 (20060101); H01L 021/44 ()

Expiration Date: 07/03/2018