Patent Number: 6,255,218

Title: Semiconductor device and fabrication method thereof

Abstract: A semiconductor device that enables to avoid short-circuit between an interconnection film and an underlying conductive region even when a contact hole is partially overlapped with an isolation insulator. A conductive region is selectively formed in an active region to be contacted therewith. An interlayer insulating film having a contact hole is formed to cover the active region and the isolation insulator. An interconnection film is formed on the interlayer insulator film to be contacted with the conductive region through the contact hole. The isolation region contains a first insulating subregion and a second insulating subregion formed on the first insulating subregion. The first insulating subregion is positioned at a deeper level than that of the second insulating subregion. The second insulating subregion may be formed in self-alignment to the first insulating subregion and may have a substantially flat surface. A part of the second insulating subregion is exposed in the contact hole so that the contact area of the interconnection film with the conductive region is partially defined by the isolation region.

Inventors: Kasai; Naoki (Tokyo, JP)

Assignee: NEC Corporation

International Classification: H01L 21/762 (20060101); H01L 21/02 (20060101); H01L 21/70 (20060101); H01L 21/60 (20060101); H01L 21/316 (20060101); H01L 21/311 (20060101); H01L 21/32 (20060101); H01L 021/311 ()

Expiration Date: 07/03/2018