Patent Number: 6,255,221

Title: Methods for running a high density plasma etcher to achieve reduced transistor device damage

Abstract: Disclosed are methods and systems for etching dielectric layers in a high density plasma etcher. A method includes providing a wafer having a photoresist mask over a dielectric layer in order to define at least one contact via hole or open area that is electrically interconnected down to the silicon substrate of the wafer. The method then proceeds to inserting the wafer into the high density plasma etcher and pulsed application a TCP power source of the high density plasma etcher. The pulsed application includes ascertaining a desired etch performance characteristic, which includes photoresist selectivity and etch rate which is associated with a continuous wave application of the TCP source. Then, selecting a duty cycle of the pulsed application of the TCP source and scaling a peak power of the pulsed application of the TCP source in order to match a cycle-averaged power that would be delivered by the continuous wave application of the TCP source. The pulsed application of the TCP power source is configured to etch through the dielectric layer to at least one contact via hole or open area while substantially reducing damage to the transistor gate oxides of the transistor devices.

Inventors: Hudson; Eric A. (Berkeley, CA), Winniczek; Jaroslaw W. (Daly City, CA), Cook; Joel M. (Pleasanton, CA), Maynard; Helen L. (Somerset, NJ)

Assignee: Lam Research Corporation

International Classification: H01L 21/02 (20060101); H01L 21/311 (20060101); H01L 021/02 ()

Expiration Date: 07/03/2018