Patent Number: 6,293,457

Title: Integrated method for etching of BLM titanium-tungsten alloys for CMOS devices with copper metallization

Abstract: Form a solder connector on a semiconductor device starting with a first step of forming at least one dielectric layer over a doped semiconductor substrate. Then form a hole through the dielectric layer down to the semiconductor substrate. Form a metal conductor in the hole. Form intermediate layers over the metal conductor and the dielectric layer. Then form a tapered opening down to the surface of the metal conductor. Form BLM layers including a titanium-tungsten (TiW) layer over the metal conductor and the dielectric layer with the remainder of the BLM layers being formed over the TiW layer. Form a mask over the top surface of the BLM layers with a patterning through hole located above the metal conductor exposing a portion of the surface of the BLM layers. Plate a C4 solder bump on the BLM layers in the patterning hole. Remove the mask. Wet etch away the BLM layers aside from the solder bump leaving a residual TiW layer over the dielectric layer. Perform a dry etching process to remove the residual TiW layer aside from the solder bump. Then, end the dry etching when the end point has been reached. Finally, heat the solder bump in a reflow process to form a C4 solder ball.

Inventors: Srivastava; Kamalesh K. (Wappingers Falls, NY), Griffith; Jonathan H. (Poughkeepsie, NY), Cullinan-Scholl; Mary C. (Hopewell Junction, NY), Brearley; William H. (Poughkeepsie, NY), Wade; Peter C. (Hyde Park, NY)

Assignee: International Business Machines Corporation

International Classification: C23F 1/26 (20060101); C23F 1/10 (20060101); H01L 21/02 (20060101); H01L 21/60 (20060101); H01L 23/485 (20060101); H01L 21/768 (20060101); H01L 21/70 (20060101); H01L 23/48 (20060101); B23K 031/02 (); B23K 031/10 ()

Expiration Date: 09/25/2018