Patent Number: 6,294,797

Title: MOSFET with an elevated source/drain

Abstract: A gate insulator layer is formed over the semiconductor substrate and a first silicon layer is then formed over the gate insulator layer. An first dielectric layer is formed over the first silicon layer. A gate region is defined by removing a portion of the gate insulator layer, of the first silicon layer, and of the first dielectric layer. A doping step using low energy implantation or plasma immersion is carried out to dope the substrate to form an extended source/drain junction in the substrate under a region uncovered by the gate region. An undoped spacer structure is formed on sidewalls of the gate region and a second silicon layer is formed on the semiconductor substrate. The first silicon layer is then removed and another doping step is performed to dope the first silicon layer and the second silicon layer. A series of process is then performed to form a metal silicide layer on the first silicon layer and the second silicon layer and also to diffuse and activate the doped dopants.

Inventors: Wu; Shye-Lin (Hsinchu, TW)

Assignee: Texas Instruments - Acer Incorporated

International Classification: H01L 21/02 (20060101); H01L 21/336 (20060101); H01L 21/28 (20060101); H01L 29/417 (20060101); H01L 29/40 (20060101); H01L 21/225 (20060101); H01L 029/72 ()

Expiration Date: 09/25/2018