Patent Number: 6,294,798

Title: Integrated circuit structure comprising capacitor element and corresponding manufacturing process

Abstract: A circuit structure for semiconductor devices which are integrated on a semiconductor layer is provided. The structure comprises at least one MOS device and at least one capacitor element that has a bottom and a top electrode. The MOS device has conduction terminals formed in the semiconductor layer, as well as a control terminal covered with an overlying insulating layer of unreflowed oxide. The capacitor element is formed on the unreflowed oxide layer.

Inventors: Zambrano; Raffaele (Viagrande, IT)

Assignee: STMicroelectronics S.r.l.

International Classification: H01L 27/115 (20060101); H01L 21/70 (20060101); H01L 21/8242 (20060101); H01L 029/04 ()

Expiration Date: 09/25/2018