Patent Number: 6,294,805

Title: Ferroelectric memory devices including capacitors located outside the active area and made with diffusion barrier layers

Abstract: Integrated circuit ferroelectric memory devices include a pair of spaced apart word lines which cross an elongated active region, a drain region in the active region between the pair of word lines, and a pair of source regions in the active region outside the pair of spaced apart word lines on opposite sides of the drain region. A pair of ferroelectric capacitors outside the elongated active region is also included, a respective one of which is adjacent a respective one of the pair of source regions. Each of the ferroelectric capacitors includes spaced apart first and second electrodes and a ferroelectric layer between them. A respective one of the first electrodes is electrically connected to a respective one of the pair of source regions. A pair of plate lines is electrically connected to a respective one of the second electrodes and a bit line is electrically connected to the drain region. Integrated circuit ferroelectric memory devices according to the invention may be formed by fabricating a field effect transistor in an integrated circuit substrate and forming a first electrode, a ferroelectric layer, a diffusion barrier layer and a second electrode on the substrate. A first patterned metal layer electrically connects the first electrode to the source region of the field effect transistor and also electrically contacts the drain region. A second patterned metal layer electrically contacts the second electrode.

Inventors: Jung; Dong-jin (Kyungki-do, KR)

Assignee: Samsung Electronics Co., Ltd.

International Classification: H01L 21/02 (20060101); H01L 27/115 (20060101); H01L 21/8246 (20060101); H01L 21/70 (20060101); H01L 27/06 (20060101); H01L 029/76 (); H01L 029/94 (); H01L 031/062 (); H01L 031/113 ()

Expiration Date: 09/25/2018