Patent Number: 6,294,807

Title: Semiconductor device structure including a tantalum pentoxide layer sandwiched between silicon nitride layers

Abstract: An insulating structure includes a first silicon nitride layer, a tantalum pentoxide layer formed above the first silicon nitride (SiN.sub.x) layer, and a second silicon nitride layer formed above the tantalum pentoxide (Ta.sub.2 O.sub.5) layer. The SiN.sub.x cladding layers prevent difflusion of the tantalum during heating. A high dielectric constant is provided. The thermal stability of the insulating structure is improved. The insulating structure may be included in a capacitor or a shallow trench isolation structure. An exemplary capacitor is formed with a substrate, a lower electrode, the three-layer Si.sub.x N.sub.y /Ta.sub.2 O.sub.5 /Si.sub.x N.sub.y structure and an upper electrode. The lower electrode may include a TiN layer formed over an aluminum layer, or a TiN layer formed over a polysilicon layer, or a polysilicon layer having an oxide barrier layer formed on it. The upper electrode may be a TiN layer or a polysilicon layer. An exemplary shallow trench isolation structure includes the Si.sub.x N.sub.y /Ta.sub.2 O.sub.5 /Si.sub.x N.sub.y structure as a liner on the sides and bottom of a shallow trench in the surface of a substrate. The shallow trench is filled with an oxide, such as TEOS. A variety of methods may be used for fabricating devices that include the Si.sub.x N.sub.y /Ta.sub.2 O.sub.5 /Si.sub.x N.sub.y structure.

Inventors: Chittipeddi; Sailesh (Allentown, PA), Pearce; Charles Walter (Emmaus, PA)

Assignee: Agere Systems Guardian Corp.

International Classification: H01L 21/02 (20060101); H01L 21/314 (20060101); H01L 27/08 (20060101); H01L 21/70 (20060101); H01L 21/318 (20060101); H01L 21/8242 (20060101); H01L 21/316 (20060101); H01L 027/108 (); H01L 029/76 (); H01L 029/94 (); H01L 031/119 (); H01L 029/00 ()

Expiration Date: 09/25/2018