Patent Number: 6,294,809

Title: Avalanche programmed floating gate memory cell structure with programelement in polysilicon

Abstract: A non-volatile memory cell structure comprises a floating gate, a reversebreakdown injection element at least partially formed in a polysiliconlayer and operatively coupled to the floating gate, and a transistor atleast partially formed in a region of a semiconductor substrate,operatively coupled to the floating gate. In a further aspect, a controlgate is capacitively coupled to the floating gate and is formed in saidpolysilicon layer. The reverse breakdown electron injection elementcomprises a first, second, and third active regions, the first and secondregions comprising a first p/n junction, the second and third activeregions comprising a second p/n junction.

Inventors: Logie; Stewart G. (Campbell, CA)

Assignee:

International Classification:

Expiration Date: 09/25/2013