Patent Number: 6,294,810

Title: EEPROM cell with tunneling at separate edge and channel regions

Abstract: An EEPROM cell is described that is programmed and erased by electrontunneling at separate regions, an edge of a tunneling drain and a sensetransistor channel. The EEPROM cell has three transistors formed in asemiconductor substrate. The three transistors are a tunneling transistor(NMOS), a sense transistor (NMOS) and a read transistor (NMOS). Electrontunneling occurs to program the EEPROM cell through a sense tunnel oxidelayer by electron tunneling across an entire portion of a sense channelupon incurrence of a sufficient voltage potential between a floating gateand the sense channel. Electron tunneling also occurs to erase the EEPROMcell through a tunnel oxide layer be electron tunneling at an edge of atunneling drain upon incurrence of a sufficient voltage potential betweenthe floating gate and the tunneling drain.

Inventors: Li; Xiao-Yu (Santa Jose, CA), Fong; Steven J. (Santa Clara, CA)


International Classification:

Expiration Date: 09/25/2013