Patent Number: 6,294,817

Title: Source/drain-on insulator (S/DOI) field effect transistor using oxidized amorphous silicon and method of fabrication

Abstract: Source and drain regions of field effect transistors are fabricated with an electrically insulating layer formed thereunder so as to reduce junction capacitance between each and a semiconductor body in which the regions are formed. Shallow trench isolation partially surrounds each transistor so as to further electrically isolate the source and drain regions from the semiconductor body. Typically for a single transistor only one surface of each drain and source region make direct contact to the semiconductor body and these surfaces are on opposite sides of a channel region of each transistor. One method of fabrication of the source and drain regions is to form an isolating isolation region around active areas in which a transistor is to be formed in a semiconductor body. Trenches separated by portions of the body are then formed in the active areas in which transistors are to be formed. On bottom surfaces of the trenches are formed an electrically insulating layer. The trenches are then filled with semiconductor material of a conductivity type opposite that of the semiconductor body. The semiconductor filled portion of each trench then serves as a drain and/or source of a field effect transistor.

Inventors: Srinivasan; Senthil (Paris, FR), Chen; Bomy (Stormville, NY)

Assignee: Infineon Technologies AG

International Classification: H01L 21/02 (20060101); H01L 21/336 (20060101); H01L 29/02 (20060101); H01L 29/06 (20060101); H01L 029/72 ()

Expiration Date: 09/25/2018