Patent Number: 6,294,819

Title: CVD Ta2O5/oxynitride stacked gate insulator with TiN gate electrode for sub-quarter micron MOSFET

Abstract: A method of fabricating a CVD Ta.sub.2 O.sub.5 /Oxynitride stacked gate insulator with TiN gate electrode for subquarter micron MOSFETs is disclosed. In a first embodiment, the surface of a silicon substrate is reacted in N.sub.2 O or NC ambient to form an oxynitride layer. Tantalum oxide is next chemical vapor deposited, thus forming a Ta.sub.2 O.sub.5 /Oxynitride stacked gate insulator. The stacked gate is then completed by depositing titanium nitride as the gate electrode and then patterning and forming the gate structure. In the second embodiment, a gate oxide is first formed on the silicon substrate. Then the gate oxide layer is nitridated in N.sub.2 O or NO ambient to form the oxynitridated layer, thus forming a two-step oxynitride layer. The tantalum oxide layer and the titanium nitride gate electrode are formed as in the first embodiment. It is disclosed in the present invention that by replacing the conventional SiO.sub.2 layer with a composite layer of Ta.sub.2 O.sub.5 /oxynitride, where the oxynitride dielectric layer is grown in a nitrogen ambient, charge trapping, interface state generation, and breakdown field distribution, the time-dependent dielectric breakdown (TDDB) of gate oxides and hence the reliability of MOSFET devices are improved substantially.

Inventors: Sun; Shi-Chung (Los Altos, CA)

Assignee: Taiwan Semiconductor Manufacturing Company

International Classification: H01L 21/02 (20060101); H01L 21/28 (20060101); H01L 29/51 (20060101); H01L 29/40 (20060101); H01L 29/49 (20060101); H01L 029/72 ()

Expiration Date: 09/25/2018