Patent Number: 6,294,833

Title: Semiconductor device and fabrication process thereof

Abstract: Described in the present invention is a semiconductor device in which a plurality of interconnect lines are disposed, through an insulating layer, on the same layer above a semiconductor substrate having a semiconductor element; a first interlevel insulator is formed selectively in a narrowly-spaced region between adjacent interconnect lines; a second interlevel insulator is formed in a widely-spaced region between said adjacent interconnect lines, and the first interlevel insulator has a smaller dielectric constant than the second interlevel insulator. According to such a constitution, strength and reliability can be heightened and performance can be improved easily even in a miniaturized interconnect structure.

Inventors: Usami; Tatsuya (Tokyo, JP)

Assignee: NEC Corporation

International Classification: H01L 21/768 (20060101); H01L 21/70 (20060101); H01L 023/48 ()

Expiration Date: 09/25/2018