Patent Number: 6,294,834

Title: Structure of combined passive elements and logic circuit on a silicon on insulator wafer

Abstract: A structure of combined passive elements and logic circuits on a SOI (Silicon On Insulator) wafer. By combining passive elements (including a resistor, an inductor and a capacitor) with a logic device on a SOI wafer with dual damascene technology, an extremely thick inductor that effectively reduces the resistance of the inductor can be formed while also reducing the layout area. The invention is compatible with conventional VLSI technology without increasing number of masks or process steps. Furthermore, because the resistor of the invention is composed of single crystal Si, the resistor has high stability and low noise. Therefore, the structure according to the invention is suitable for RF device design and is also suitable for a System On Chip design.

Inventors: Yeh; Wen-Kuan (Chupei, TW), Lin; Chih-Yung (Taichung Hsien, TW)

Assignee: United Microelectronics Corp.

International Classification: H01L 21/02 (20060101); H01L 23/48 (20060101); H01L 23/482 (20060101); H01L 27/12 (20060101); H01L 029/40 (); H01L 027/01 (); H01L 029/00 (); H01L 023/52 (); H01L 023/48 ()

Expiration Date: 09/25/2018