Patent Number: 6,294,836

Title: Semiconductor chip interconnect barrier material and fabrication method

Abstract: A microelectronic semiconductor interconnect structure barrier and methodof deposition provide improved conductive barrier material properties forhigh-performance device interconnects. The barrier comprises a dopantselected from the group consisting of platinum, palladium, iridium,rhodium, and tin. The barrier can comprise a refractory metal selectedfrom the group consisting of tantalum, tungsten titanium, chromium, andcobalt, and can also comprise a third element selected from the groupconsisting of carbon, oxygen and nitrogen. The dopant and other barriermaterials can be deposited by chemical-vapor deposition to achieve goodstep coverage and a relatively conformal thin film with a good nucleationsurface for subsequent metallization such as copper metallization in oneembodiment, the barrier suppresses diffusion of copper into other layersof the device, including the inter-metal dielectric, pre-metal dielectric,and transistor structures.

Inventors: Paranjpe; Ajit P. (Sunnyvale, CA), Moslehi; Mehrdad M. (Los Altos, CA), Bubber; Randhir S. (San Ramon, CA), Velo; Lino A. (San Ramon, CA)


International Classification:

Expiration Date: 09/25/2013