Patent Number: 6,294,840

Title: Dual-thickness solder mask in integrated circuit package

Abstract: Provided is a two-step, dual-thickness solder mask material on the substrate surface. The material is preferably applied in a series of screenings: A first screening of the solder mask material in the region where the chip will be placed, and a second screening of solder mask surrounding the place on the substrate surface where the die will be placed, normally over the outside edge regions of the substrate surface. The thickness of this first screening of solder mask may be from about 10 to 20 microns, while the thickness of the second screening of solder mask is about conventional thickness for a solder mask, for example from about 30 to 40 microns.

Inventors: McCormick; John P. (Palo Alto, CA)

Assignee: LSI Logic Corporation

International Classification: H01L 21/02 (20060101); H01L 21/56 (20060101); H05K 3/28 (20060101); H05K 3/34 (20060101); H01L 023/48 (); H01L 023/52 (); H01L 029/40 ()

Expiration Date: 09/25/2018