Patent Number: 6,294,921

Title: Apparatus for testing an integrated circuit device

Abstract: A method and apparatus for contact testing a plurality of devices under test, either sequentially or simultaneously. In a first test phase it is determined whether the test probe to each contact is shorted to the most negative rail. In a second phase it is determined whether the test probe has made proper contact, and whether ESD diodes on the devices under test are functional. In both test phases a negative pulse is generated on a tester bus and applied to the contact by the test probe. In the first test phase the positive rail of the device under test is grounded; in the second test phase the positive rail of the device under test is made positive. The negative rail of the device under test is connected to the negative rail of the tester. In both test phases, upon termination of the negative pulse, the bus is restored to a positive voltage which is dependent upon the condition of the contact and the condition of expected input devises at the contact. The bus voltage as measured in accordance with a logic which determines the condition of the contact and the condition of expected input devices at the contact. Data signals for functional testing of the device under test are can be applied to the bus through an isolating driver which preserves he bolt of the contact test.

Inventors: Bonaccio; Anthony R. (Shelburne, VT), Leighton; Howard J. (Underhill, VT)

Assignee: International Business Machines Corp.

International Classification: G01R 31/02 (20060101); G01R 31/04 (20060101); G01R 001/073 (); G01R 031/04 ()

Expiration Date: 09/25/2018