Patent Number: 6,294,926

Title: Very fine-grain field programmable gate array architecture and circuitry

Abstract: A very fine-grained gate array cell is provided that includes a two-inputlogic device and a cascade NAND gate with buffered output. The NAND gateaccepts a cascade input from another cell, and the cascade output of theNAND gate is provided as a cascade input to the other cell to facilitatethe efficient implementation of cross-coupled devices. Each cell containsintegral routing paths that facilitate a "sea of cells" layout approach.To ease the routing task, the output of each gate array cell is pre-wiredso as to facilitate a programmed interconnection to each logic input ofadjacent cells, near-adjacent cells, and far cells, and the aforementionedcascade interconnection with adjacent upper and lower cells. Thisconfiguration allows adjacent and near-adjacent cells to be easilyinterconnected to form macro cells that conform to higher level functionalblocks. The gate array does not contain explicit routing channels; routingis effected using the prewired routing that is integral with each gatearray cell.

Inventors: Cline; Ronald L. (Albuquerque, NM)


International Classification:

Expiration Date: 09/25/2013