Patent Number: 6,294,929

Title: Balanced-delay programmable logic array and method for balancing programmable logic array delays

Abstract: Balanced-delay programmable logic array and a method for balancing programmable logic array delays provide improved performance in circuits employing programmable logic. By adding transistors to the programming plane that do not form part of the logic implementation, the capacitance on each of the input logic lines can be balanced, substantially reducing the skew between signals entering the final logic gates. This provides programmable logic arrays that may implement asynchronous logic in applications where skew was previously prohibitive and further increases the reliability of state evaluations in synchronous logic.

Inventors: Coulman; Paula Kristine (Austin, TX), Dhong; Sang Hoo (Austin, TX), Park; Jaehong (Austin, TX), Posluszny; Stephen Douglas (Round Rock, TX), Takahashi; Osamu (Round Rock, TX)

Assignee: International Business Machines Corporation

International Classification: H03K 19/177 (20060101); H03K 019/177 (); H03H 011/26 ()

Expiration Date: 09/25/2018