Patent Number:
6,294,935
Title:
Built-in-self-test circuitry for testing a phase locked loop circuit
Abstract:
A built-in-self-test circuit aids in testing a phase locked loop circuit. The phased locked loop has a plurality of frequency multipliers. The built-in-self-test circuit includes a frequency divider and a multiplexer. The frequency divider has a plurality of divide-by-counters. For each frequency multiplier within the plurality of frequency multipliers there is a corresponding divide-by-counter. A ratio of a multiplier for each frequency multiplier to a divider of its corresponding divide-by-counter is a constant for all frequency multipliers and corresponding divide-by-counters. When a frequency multiplier within the plurality of frequency multipliers is selected, the multiplexer selects its corresponding divide-by-counter to produce a test output clock.
Inventors:
Ott; Russell George (East Brunswick, NJ)
Assignee:
VLSI Technology, Inc.
International Classification:
G01R 31/28 (20060101); G01R 31/3183 (20060101); G01R 31/3187 (20060101); H03L 7/16 (20060101); H03L 007/06 ()
Expiration Date:
09/25/2018