Patent Number: 6,294,936

Title: Spread-spectrum modulation methods and circuit for clock generatorphase-locked loop

Abstract: A spread-spectrum modulation method and circuit for a clock generatorphase-locked loop (PLL). A dither signal is injected into a PLL insynchronization with and having the same period or fraction of the sameperiod as the phase comparison performed within the PLL. Over such period,the phase error caused by the modulation will integrate to zero and henceavoid transmitting a disturbance to the loop. A particular embodimentutilizes an output of the reference divider and/or feedback divider withinthe PLL to generate the dither signal. Such a configuration avoids theneed for additional hardware which otherwise would increase the chip areaand/or cost of the device. The reference divider and/or feedback divideris made up preferably of a linear feedback shift register (LFSR). One ormore stages of the LFSR provide an output which is used to generate thedither signal. In a preferred embodiment, the output from the LFSRexhibits a pseudo-random sequence.

Inventors: Clementi; Daniel M. (Doylestown, PA)


International Classification:

Expiration Date: 09/25/2013