Patent Number: 6,294,937

Title: Method and apparatus for self correcting parallel I/O circuitry

Abstract: 3An optimal delay value, usually the mid-delay in the operational window, for the data signal may be retained as a way of shifting the skew of the clock on all data lines at the same time. That delay value may be stored in a memory and converted to a control voltage for controlling a digitally controlled voltage variable delay to adjust the delay for data in a bus. The digitally controlled voltage variable delay contains a number of individual delay units which are selectively activated by the control voltage from the value stored in memory. A phase locked loop is employed to ensure that variations due to voltage, temperature, and processing are minimized.

Inventors: Crafts; Harold S. (Colorado Springs, CO), Steele; David P. (Colorado Springs, CO)

Assignee: LSI Logic Corporation

International Classification: G06F 13/42 (20060101); H03L 007/06 ()

Expiration Date: 09/25/2018