Patent Number: 6,294,938

Title: System with DLL

Abstract: A system (50) has a shifting delay circuit (60) which provides a variable delay for delaying a source clock and a delay locked loop (DLL) (70) which includes a delay line (72) which provides a variable delay for delaying the source clock. The delay line (18) has its delay varied by a counter (74). The counter (74) is incremented in order to change the delay. The shifting delay circuit (60) is based on half periods of a reference clock (GCLK) which has a known relationship to the source clock. The total delay for the source clock is a combination of that provided by shifting delay circuit (60) and delay line (72). The delay line (72), which requires relatively large amounts of die area in an integrated circuit can be smaller in size due to the usage of shifting delay circuit (60).

Inventors: Coddington; John Deane (Cedar Park, TX), Hui; Chau-Shing (Austin, TX)

Assignee: Motorola, Inc.

International Classification: G06F 1/10 (20060101); H03L 7/07 (20060101); H03L 7/081 (20060101); H03L 7/08 (20060101); H03L 7/089 (20060101); H03L 007/06 ()

Expiration Date: 09/25/2018