Patent Number: 6,294,940

Title: Symmetric clock receiver for differential input signals

Abstract: A clock circuit, in accordance with the present invention, includes a first circuit stage for providing a first output signal and a second output signal. The first circuit stage includes inputs for clock signals. A switch is coupled to the first stage for switching an output polarity by selecting one of the first output signal and the second output signal generated by the first circuit stage in accordance with a control signal. A second circuit stage is coupled to the first circuit stage through the switch. The second circuit stage for shaping the first and second output signals input thereto from the switch. The second circuit stage includes an output for outputting clock pulses based on the first and second output signals. The control signal is generated from the clock pulses.

Inventors: Kiehl; Oliver (Charlotte, VT)

Assignee: Infineon Technologies North America Corp.

International Classification: G06F 1/10 (20060101); H03K 5/1534 (20060101); H03K 5/00 (20060101); H03K 5/153 (20060101); H03K 003/00 ()

Expiration Date: 09/25/2018