Patent Number: 6,294,943

Title: Method of designing fail-safe CMOS I/O buffers whose external nodes accept voltages higher than the maximum gate oxide operating voltage

Abstract: A fail-safe Input/Output buffer bias circuit for digital CMOS chips provides protection for Input/Output buffers which have high voltages applied to the Input/output node and are subjected to power supply failure resulting in a collapsing supply voltage decaying to zero volts while said Input/output circuit has a high voltage remaining applied to its Input/output node. The Input/output buffer bias circuit is comprised of a sensing circuit and a bias generator circuit which acts to drive protection transistors in a manner which optimally minimizes the voltage impressed on input or output devices under all conditions which could persist in the event of V.sub.DD supply voltage failure. Protection circuitry holds all three combinations of voltage stress, gate-to-source, gate-to-drain, and drain-to-source voltages, to acceptable levels.

Inventors: Wall; Frederick G. (Garland, TX), Andresen; Bernhard H. (Dallas, TX)

Assignee: Texas Instruments Incorporated

International Classification: H03K 19/007 (20060101); H03K 19/003 (20060101); H02H 009/00 (); H03K 019/018 ()

Expiration Date: 09/25/2018