Patent Number: 6,294,944

Title: Interface circuit and interface circuit delay time controlling method

Abstract: An interface cell transmits a signal with a delay time corresponding to adelay time control signal. A delay time control circuit consists of adelay chain and a PLL circuit. The delay chain consists of a plurality ofseries-connected interface cells to a head cell of which a clock signal issupplied, and a delay signal of a clock signal is then fetched from theinterface cell at an arbitrary stage. The PLL circuit generates a delaytime control signal so as to make phase difference between the clocksignal and the delay signal equal. This is true of a delay cell. A phasedifference compensation circuit is provided on an output end of a clockline of the integrated circuit to delay an input clock signal based on aninput control signal. A phase difference detection circuit receives anoutput signal of a flip-flop provided on an output end of a data line ofthe integrated circuit and an output signal of the phase differencecompensation circuit, detects phase difference between both output signalsand outputs the control signal in response to the phase difference.

Inventors: Shiochi; Masuzumi (Tokyo, JP), Egawa; Kanji (Tokyo, JP)


International Classification:

Expiration Date: 09/25/2013