Patent Number: 6,294,960

Title: Phase lock loop circuit using signal estimator

Abstract: A signal estimator estimates a transmission signal series using Viterbialgorithm, and outputs an estimated signal and a minimum path metricsignal. A switching unit is controlled by a control signal in such amanner that, for a certain period from the start of the operation of PLLwhich requires quick response, a minimum path metric history signal isselected, while, in the other case, an estimated signal is selected. Areplica generator generates a replica signal using a signal output fromthe switching unit. The generation of the replica signal using the pathmetric history signal offers quick response, but on the other hand, theaccuracy is low. On the other hand, the use of the estimated signal offershigh accuracy, but on the other hand, the response speed is low. Thus, aphase change contained in a received signal is corrected in a highlyaccurate and quick manner.

Inventors: Omori; Youko (Tokyo, JP)


International Classification:

Expiration Date: 09/25/2013