Patent Number: 6,295,016

Title: Pipeline analog to digital (A/D) converter with relaxed accuracy requirement for sample and hold stage

Abstract: A pipeline analog to digital (A/D) converter for converting an analog input signal into a digital representation of the analog signal. The pipeline A/D converter has a sample and hold stage, the sample and hold stage sampling and holding the analog input signal and outputting a sampled and held signal. The pipeline A/D converter also has a first analog signal converter stage, the first analog converter stage producing a digital output based on the sampled and held signal, from which a most significant bit of the digital representation of the analog input signal is derived. The first analog converter stage produces a residue signal based on a comparison of the analog input signal and an analog representation of the digital output. The pipeline A/D converter has at least one additional stage, the additional stage producing a subsequent digital output based on the residue signal produced by the first analog signal converter stage, at least one bit which is less significant than the most significant bit being derived from the subsequent digital output.

Inventors: Chiang; Meei-Ling (San Jose, CA)

Assignee: Advanced Micro Devices, Inc.

International Classification: H03M 1/06 (20060101); H03M 1/44 (20060101); H03M 1/38 (20060101); H03M 001/38 ()

Expiration Date: 09/25/2018