Patent Number: 6,295,074

Title: Data processing apparatus having DRAM incorporated therein

Abstract: The present invention can be introduced to an architecture such as a personal computer or an amusement equipment for realizing a high-speed graphic processing. In the case where a frame buffer, a command memory and an image processor are integrated in one chip in order to improve the drawing performance of an image processing device, each of the frame buffer and the command memory is constructed by a plurality of identical memory modules and the same row address is allotted to each memory module, thereby increasing the memory address depth. Thereby, it is possible to realize an incorporated frame buffer and an incorporated command memory each of which has a large capacity when seen from the image processor.

Inventors: Yamagishi; Kazushige (Higashimurayama, JP), Sato; Jun (Musashino, JP), Miyamoto; Takashi (Tokyo, JP)

Assignee: Hitachi, Ltd.

International Classification: G09G 5/36 (20060101); G06T 1/20 (20060101); G06F 015/76 ()

Expiration Date: 09/25/2018