Patent Number: 6,295,142

Title: Semiconductor apparatus and method for producing it

Abstract: In order to prevent a decrease of yield due to a discontinuity of a wire or a short between upper and lower metal wires in production of a TFT matrix panel having pixel capacitors and TFTs and produce the TFT panel in a good yield without decrease of an aperture rate of the pixel capacitor portions even with increase in the size of the panel and with micronization of the pixel pattern, ends of bias lines on the opposite side to connection to a common electrode driver for application of bias are electrically connected to each other by a redundant wire.

Inventors: Watanabe; Minoru (Sagamihara, JP), Mochizuki; Chiori (Sagamihara, JP), Ishii; Takamasa (Atsugi, JP)

Assignee: Canon Kabushiki Kaisha

International Classification: G02F 1/13 (20060101); G02F 1/1362 (20060101); G09G 3/36 (20060101); H04N 001/04 ()

Expiration Date: 09/25/2018