Patent Number:
6,295,218
Title:
Semiconductor device
Abstract:
A memory device having a plurality of blocks, each of a plurality of blocks comprising a memory array having a plurality of word lines and a plurality of memory cells connected to the word lines, an associative cell array for outputting a hit signal by comparing a first address inputted thereto with internal data and a decoder circuit for selecting one line by decoding a second address and wherein one of the word lines is selected based on the line selected by the decoder circuit and the hit signal.
Inventors:
Osada; Kenichi (San Jose, CA), Ishibashi; Koichiro (Warabi, JP)
Assignee:
Hitachi, Ltd.
International Classification:
G11C 15/00 (20060101); G11C 015/00 ()
Expiration Date:
09/25/2018