Patent Number: 6,295,222

Title: Semiconductor memory device with two layers of bit lines

Abstract: A semiconductor memory device according to the present invention comprises, in general, a memory cell array, a plurality of first-layer and second-layer bit lines. The memory cell array includes a matrix of memory cells arranged along a line and row directions, each memory cell being formed within a memory cell region. Each of first-layer bit lines is extending along the row direction, and provided on a plurality of the memory cell regions. Each of second-layer bit lines is connected with the first-layer bit line via a connecting hole. The memory cell regions include first and second memory cell regions, the first memory cell region is provided with the connecting hole, the second memory cell region is not provided with the connecting hole. Also, at least one of the memory cells formed within the first memory cell regions is a dummy cell incapable of electrically serving as the normal memory cell.

Inventors: Higashide; Yoshiko (Tokyo, JP), Ohbayashi; Shigeki (Tokyo, JP)

Assignee: Mitsubishi Kabushiki Kaisha

International Classification: G11C 7/18 (20060101); G11C 7/00 (20060101); G11C 5/06 (20060101); G11C 005/06 ()

Expiration Date: 09/25/2018