Patent Number: 6,295,224

Title: Circuit and method of fabricating a memory cell for a static random access memory

Abstract: A circuit and method is disclosed for a memory cell for a static random access memory. The memory cell includes a pair of cross-coupled CMOS logic inverters that are connected together to form a latch, and a pair of p-channel transmission gate transistors that are connected to the logic inverters for selectively providing access to the latch. The layout of the memory cell includes a rectangular active area in which the p-channel transistors of the memory cell are located. The rectangular active area abuts a similar active area of an adjacent memory cell along a row of memory cells so as to form a single rectangular active area for the p-channel memory cell transistors. The rectangular active area reduces the occurrence of fabrication-related phenomena that adversely effect the performance of the memory cell.

Inventors: Chan; Tsiu Chiu (Carrollton, TX), Zamanian; Mehdi (Carrollton, TX), McClure; David Charles (Carrollton, TX)

Assignee: STMicroelectronics, Inc.

International Classification: G11C 11/412 (20060101); H01L 21/70 (20060101); H01L 21/8244 (20060101); G11C 011/00 ()

Expiration Date: 09/25/2018